The basic design unit that describes the hardware using Verilog is the module. The construction of complex electronic circuits is mainly achieved through the interconnection of modules. Modules are included in the keyword module, endmodule. The actual circuit components. The modules in Verilog are similar to the functions in C language. They can provide input and output ports, and can call other modules as examples, or can be called by other module instances. The combination logic portion and the process timing portion may be included in the module. For example, a four-choice multiplexer can be described by a module. It has two bit-selected input signals, four data inputs, and one output, which can be expressed in Verilog as: Module mux (out, select, in0, in1, in2, in3);output out;input [1:0] select;input in0, in1, in2, in3;//specific register transfer level code endmodule Designers can use a top-level module to test the module by calling the above module. This top-level module is often referred to as the "Testbench." In order to maximize the functional verification of the logic of the circuit, the test code needs to cover as much of the statements, branches, conditions, paths, triggers, and state machine states involved in the system as possible. The verifier needs to create enough inputs in the test platform. Motivate and connect to the input of the module under test, and then check whether the performance of its output is as expected (such as SystemVerilog's hardware verification language can provide a data structure optimized for verification, verified by random test, which is highly complex The verification of integrated circuit design can play a key role). When an instance calls a module, the connection of the ports needs to be arranged in the order in which they are declared. This top-level module does not need to be called by the outside world, so there is no input/output port: Module tester;reg [1:0] SELECT;reg IN0, IN1, IN2, IN3;wire OUT;mux my_mux (OUT, SELECT, IN0, IN1, IN2, IN3); //The instance calls the mux module, this instance is named For my_muxiniTIal // need to emulate the motivation code begin endendmodule In this test platform module, the designer can set the input signal and signal monitoring program during simulation, and then observe whether the output of the simulation meets the requirements, so that you can understand whether the design has reached the expected level. When an instance reference is made to a module in the example, the input variables are listed in the order in which they were declared. In addition, you can use or use a named port connection. In this way, the order of the ports can be different from the original module declaration, or even some ports can be disconnected: Mux my_mux (.out(OUT), .select(SELECT), .in0(IN0), .in1(IN1), .in2(IN2), .in3(IN3));//use a named port connection, outside the parentheses The port when the module is declared. The actual port connection in parentheses is equivalent to the formal parameter of C language in parentheses. The parentheses are equivalent to the actual parameter endmodule. The situation described above is that the test variables of the top module of the test platform are directly connected to the designed functional modules. The test platform can also be in another form, that is, the test platform does not directly connect to the designed function module, but under the test platform, the excitation module and the function module are connected to each other through the wire network at the same level of abstraction. Both types of test platforms can be tested on functional modules. Large-scale circuit systems are connected and called by modules at different levels to achieve complex functions. Verilog code Module alarm_block ( Input wire rst, Clk, Hrs, Mins, Alarm, Output wire [4:0] alarm_hr, Output wire [5:0] alarm_min ); Wire hour_s, min_s; Alarm_counter counter1 ( rst, hour_s, min_s, clk, alarm_hr, alarm_min ); State_machine alarm_state ( rst, alarm, hrs, mins, clk, hour_s, min_s ); Endmodule Module state_machine ( Input wire rst, Alarm, Hrs, Mins, Clk, Output reg hrs_out, Mins_out ); Parameter IDLE = 2'b00, SET_HRS = 2'b01, SET_MINS = 2'b11; Reg[1:0] state, next; Always@( posedge clk or posedge rst ) If( rst ) State "= IDLE; Else state Always@( alarm or hrs or mins or state ) Case( state ) IDLE: If( !alarm ) begin Next = IDLE; Hrs_out = 0; Mins_out = 0; End else if ( alarm & hrs & !mins ) begin Next = SET_HRS; Hrs_out = 1; Mins_out = 0; End Else if( alarm & !hrs & mins ) begin Next = SET_MINS; Hrs_out = 0; Mins_out = 1; End SET_HRS : begin If( alarm & hrs & !mins ) begin Next = SET_HRS; Hrs_out = 1; End else begin next = IDLE; Hrs_out = 0; End Mins_out = 0; End SET_MINS : begin If( alarm & !hrs & mins ) begin Next = SET_MINS; Mins_out = 1; End Else begin Next = IDLE; Mins_out = 0; End Hrs_out = 0; End Default : begin Next = 2'bx; Hrs_out = 1'bx; Mins_out = 1'bx; End Endcase Endmodule Module alarm_counter ( Input wire rst, Hr_set, Min_set, Clk, Output reg [4:0] hrs, Output reg [5:0] mins ); //set alarm minutes Always@ ( posedge clk or posedge rst ) If( rst ) Mins "= 0; Else if( min_set & !hr_set ) If( mins == 6'b111011 ) Mins "= 6'b0; Else Mins <<= mins + 6'b000001; //set alarm hours Always@ ( posedge clk or posedge rst ) If( rst ) Hrs "= 0; Else if( hr_set & !min_set) If ( hrs == 5'b10111 ) Hrs "= 5'b0; Else Hrs "= hrs + 5'b00001; Endmodule Module Alarm_sm_2 ( Input wire rst, Clk, Compare_in, Toggle_on, Output reg ring ); Parameter IDLE = 1'b0, ACTI = 1'b1; Reg state, next; Always@ ( posedge clk or posedge rst ) If ( rst ) State "= IDLE; Else State "= next; Always@ ( state or compare_in or toggle_on ) Case ( state ) IDLE: If( toggle_on & compare_in ) begin Next "= ACTI; Ring "= 1; End Else begin Next "= IDLE; Ring "= 0; End ACTI: If( toggle_on ) begin Next "= ACTI; Ring "= 1; End Else begin Next "= IDLE; Ring "= 0; End Default : begin Next =" 1'bx; Ring "= 1'bx; End Endcase Endmodule Module comparator ( Input wire [4:0] alarm_hr, Time_hr, Input wire [5:0] alarm_min, Time_min, Output reg compare_out ); Always@ ( * ) If( ( alarm_hr == time_hr ) && ( alarm_min == time_min ) ) Compare_out = 1; Else compare_out = 0; Endmodulemodule convertor_ckt ( Input [4:0]hour, Input [5:0]min, Output [13:0]disp1, disp2 ); Wire [13:0] disp1_0; Segment_decoder segment_decoder_hr ( {1'b0, hour}, disp1_0 ); Segment_decoder segment_decoder_min ( min , disp2 ); Hours_filter filter ( disp1_0, disp1 ); Endmodule Module segment_decoder ( Input wire [5:0] num, Output reg [13:0] disp ); Always@ ( num ) Case ( num ) 6'b000000 : disp = 14'b0111111_0111111; 6'b000001 : disp = 14'b0111111_0000110; 6'b000010 : disp = 14'b0111111_1011011; 6'b000011 : disp = 14'b0111111_1001111; 6'b000100 : disp = 14'b0111111_1100110; 6'b000101 : disp = 14'b0111111_1101101; 6'b000110 : disp = 14'b0111111_1111101; 6'b000111 : disp = 14'b0111111_0000111; 6'b001000 : disp = 14'b0111111_1111111; 6'b001001 : disp = 14'b0111111_1101111; 6'b001010 : disp = 14'b0000110_0111111; 6'b001011 : disp = 14'b0000110_0000110; 6'b001100 : disp = 14'b0000110_1011011; 6'b001101 : disp = 14'b0000110_1001111; 6'b001110 : disp = 14'b0000110_1100110; 6'b001111 : disp = 14'b0000110_1101101; 6'b010000 : disp = 14'b0000110_1111101; 6'b010001 : disp = 14'b0000110_0000111; 6'b010010 : disp = 14'b0000110_1111111; 6'b010011 : disp = 14'b0000110_1101111; 6'b010100 : disp = 14'b1011011_0111111; 6'b010101 : disp = 14'b1011011_0000110; 6'b010110 : disp = 14'b1011011_1011011; 6'b010111 : disp = 14'b1011011_1001111; 6'b011000 : disp = 14'b1011011_1100110; 6'b011001 : disp = 14'b1011011_1101101; 6'b011010 : disp = 14'b1011011_1111101; 6'b011011 : disp = 14'b1011011_0000111; 6'b011100 : disp = 14'b1011011_1111111; 6'b011101 : disp = 14'b1011011_1101111; 6'b011110 : disp = 14'b1001111_0111111; 6'b011111 : disp = 14'b1001111_0000110; 6'b100000 : disp = 14'b1001111_1011011; 6'b100001 : disp = 14'b1001111_1001111; 6'b100010 : disp = 14'b1001111_1100110; 6'b100011 : disp = 14'b1001111_1101101; 6'b100100 : disp = 14'b1001111_1111101; 6'b100101 : disp = 14'b1001111_0000111; 6'b100110 : disp = 14'b1001111_1111111; 6'b100111 : disp = 14'b1001111_1101111; 6'b101000 : disp = 14'b1100110_0111111; 6'b101001 : disp = 14'b1100110_0000110; 6'b101010 : disp = 14'b1100110_1011011; 6'b101011 : disp = 14'b1100110_1001111; 6'b101100 : disp = 14'b1100110_1100110; 6'b101101 : disp = 14'b1100110_1101101; 6'b101110 : disp = 14'b1100110_1111101; 6'b101111 : disp = 14'b1100110_0000111; 6'b110000 : disp = 14'b1100110_1111111; 6'b110001 : disp = 14'b1100110_1101111; 6'b110010 : disp = 14'b1101101_0111111; 6'b110011 : disp = 14'b1101101_0000110; 6'b110100 : disp = 14'b1101101_1011011; 6'b110101 : disp = 14'b1101101_1001111; 6'b110110 : disp = 14'b1101101_1100110; 6'b110111 : disp = 14'b1101101_1101101; 6'b111000 : disp = 14'b1101101_1111101; 6'b111001 : disp = 14'b1101101_0000111; 6'b111010 : disp = 14'b1101101_1111111; 6'b111011 : disp = 14'b1101101_1101111; Default : disp = 14'bx; Endcase Endmodule Module Hours_filter ( Input wire [13:0] num, Output reg [13:0] num_disp ); Always@ ( * ) If ( num[13:7] == 7'b011_1111 ) Num_disp = { 7'b0, num[6:0] }; Else Num_disp = num; Endmodule Module Mux ( Input wire alarm, Mode, Input wire [4:0]alarm_hr, Time_hr, Input wire [5:0]alarm_min, Time_min, Output reg [1:0]am_pm_display, Output reg [4:0]hours, Output reg [5:0]minutes ); Always@( * ) begin //output hours and minutes Hours = alarm ? Alarm_hr : time_hr Minutes = alarm ? Alarm_min : time_min; //12hours system or 24hours system and set am_pm_display If ( mode ) Case ( hours ) 0 : begin am_pm_display = 2'b10; hours = 5'b01100; end 1 : am_pm_display = 2'b10; 2 : am_pm_display = 2'b10; 3 : am_pm_display = 2'b10; 4 : am_pm_display = 2'b10; 5 : am_pm_display = 2'b10; 6 : am_pm_display = 2'b10; 7 : am_pm_display = 2'b10; 8 : am_pm_display = 2'b10; 9 : am_pm_display = 2'b10; 10: am_pm_display = 2'b10; 11: am_pm_display = 2'b10; 12: am_pm_display = 2'b01; 13: begin am_pm_display = 2'b01; hours = 5'b00001 end 14: begin am_pm_display = 2'b01; hours = 5'b00010 end 15: begin am_pm_display = 2'b01; hours = 5'b00011 end 16: begin am_pm_display = 2'b01; hours = 5'b00100 end 17: begin am_pm_display = 2'b01; hours = 5'b00101 end 18: begin am_pm_display = 2'b01; hours = 5'b00110 end 19: begin am_pm_display = 2'b01; hours = 5'b00111 end 20: begin am_pm_display = 2'b01; hours = 5'b01000 end 21: begin am_pm_display = 2'b01; hours = 5'b01001 end 22: begin am_pm_display = 2'b01; hours = 5'b01010 end 23: begin am_pm_display = 2'b01; hours = 5'b01011 end Default: begin am_pm_display = 2'bx; hours = 5'bx; end Endcase Else Am_pm_display = 2'b00; End Endmodule Module time_block ( Input wire rst, Clk, Hrs, Mins, Set_time, Output wire [4:0] time_hr, Output wire [5:0] time_min, Time_sec ); Wire hour_s, min_s; Time_counter counter2 ( rst, hour_s, min_s, clk, time_hr, time_min, time_sec ); State_machine time_state ( rst, set_time, hrs, mins, clk, hour_s, min_s ); Endmodule Module time_counter ( Input wire rst, Hr_set, Min_set, Clk, Output reg [4:0] hrs, Output reg [5:0] mins, Secs ); Always@ ( posedge clk or posedge rst ) If( rst ) Secs "= 0; Else if( secs == 6'b111011 ) Secs == 6'b0; Else Secs "= secs + 6'b000001; Always@ ( posedge clk or posedge rst ) If( rst ) Mins "= 0; Else if( (min_set & !hr_set) || (!hr_set & !min_set & (secs == 6'b111011)) ) If( mins == 6'b111011 ) Mins "= 6'b0; Else mins "= mins + 6'b000001; Always@ ( posedge clk or posedge rst ) If( rst ) Hrs "= 0; Else if( (hr_set & !min_set) ||(!hr_set & !min_set & (secs == 6'b111011) & (mins == 6'b111011)) ) If( hrs == 5'b10111 ) Hrs "= 5'b0; Else Hrs "= hrs + 5'b00001; Endmodule Module timer ( Input wire rst, Clk, Alarm, Set_time, Hrs, Mins, Toggle_switch, Mode, Output wire speaker_out, Output wire [1:0]am_pm_display, Output wire [13:0] disp1, Disp2 ); Wire [5:0] time_min, time_sec, alarm_min, min; Wire [4:0] time_hr, alarm_hr, hour; Wire compare; Time_block time_mod ( rst, clk, hrs, mins, set_time, time_hr, time_min, time_sec ); Alarm_block alarm_mod ( rst, clk, hrs, mins, alarm, alarm_hr, alarm_min ); Comparator comparator_mod ( alarm_hr, time_hr, alarm_min, time_min, compare ); Alarm_sm_2 bell_mod ( rst, clk, compare, toggle_switch, speaker_out ); Mux mux_mod ( alarm, mode, alarm_hr, time_hr, alarm_min, time_min, am_pm_display, hour, min ); Convertor_ckt convertor_mod ( hour, min, disp1, disp2 ); Endmodule Module top; Reg rst, clk, alarm, set_time, hrs, mins, toggle_switch, mode; Wire [1:0] am_pm_display; Wire speaker_out; Wire [13:0] disp1, disp2; Timer electronic_watch( rst, clk, alarm, set_time, hrs, mins, toggle_switch, mode, speaker_out, am_pm_display, disp1, disp2 ); Always begin Clk = 0; #10 clk = 1; #10; End Initial begin $monitor($time,,,,"disp1=%b disp2=%b am_pm_display=%b speaker_out=%b", disp1, disp2, am_pm_display, speaker_out ); Rst = 0; Alarm = 0; Set_time = 0; Hrs = 0; Mins = 0; Toggle_switch = 0; Mode = 0; #5 rst = 1; //reset #4 rst = 0; #3000 mode = 1;//12hours system display #3000 mode = 0;//24hours system display #1200 alarm = 1; mins = 1;//set alarm minutes #200 mins = 0; toggle_switch = 1;//switch on #100 alarm = 0; #10000 toggle_switch = 0;//switch off #10000 set_time = 1; hrs = 1;//set hours #40 hrs = 0; #20 mins = 1;//set minutes #200 set_time = 0; mins =0; #40 alarm = 1; hrs = 1;//set alarm hours #40 hrs = 0; #20 mins = 1;//set alarm minutes #800 mins = 0; toggle_switch = 1; #300 alarm = 0; #24000 set_time = 1; hrs = 1;toggle_switch = 0;//set hours #240 set_time = 0; hrs = 0; #40 mode = 1; //12hours system display End Endmodule Explosion-proof Screen Protector The Explosion-proof Screen Protective Film for mobile phones is a protective film that can effectively buffer the impact, prevent the screen from bursting, or prevent the glass panel from being broken and scattered due to accidental impact of the mobile phone. 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