With the rapid development of very large-scale integrated circuits, the semiconductor industry has entered the deep sub-micron era. The feature size of devices is getting smaller and smaller, and the chip scale is getting larger and larger. It is possible to integrate millions to hundreds of millions of transistors on a single chip. Such a dense integration allows us to integrate the functions previously implemented by several chips such as CPU and peripherals on a small chip. A single integrated circuit constitutes a powerful and complete system. This is what we usually So-called system-on-chip. IP multiplexing is one of the core technologies in the system-on-chip era. Since the designs of IP cores are very different, if they can be directly connected, they must comply with the same interface standards. In the system-on-chip, the processor core and all peripherals are interconnected through a shared bus, so these IP cores must comply with the same bus specification. The bus specification defines a common interface between IP cores, so it defines a set of standard signals and bus cycles to connect different modules, rather than trying to standardize the functions and interfaces of IP cores. An on-chip bus (On-Chip Bus, OCB) specification generally needs to define the relationships between the drivers, timing, strategies, etc. in the process of initialization, arbitration, request transmission, response, sending and receiving between various modules. The resource and environment of the chip and the circuit board are different, resulting in several obvious differences between the on-chip bus and the on-board bus, including: â‘ On-chip buses mostly use unidirectional signal lines, while on-board buses mostly use three-state signals. The on-chip tri-state bus has great defects in terms of power consumption, speed, and testability, and once a multi-drive situation occurs, the chip will be destroyed (for example, if the signal that should output "Z" is actually output as "1", and the other If a signal output is "0", a low-resistance path is formed, resulting in excessive local current and difficulty in releasing heat in time, thereby increasing chip power consumption and greatly reducing chip life). Due to the abundant on-chip wiring resources, the on-chip bus mostly uses unidirectional signal lines. Because the wiring resources on the circuit board are relatively expensive, the on-board bus mostly uses a tri-state bus. However, due to the power consumption and speed limitation of the tri-state bus, the current on-board bus is also developing in the direction of serial and non-tri-state, such as USB And PCI Express. â‘¡On-chip bus is simpler and more flexible than on-board bus. First, the on-chip bus structure should be simple, which can take up fewer logic units; second, the timing should be simple to help increase the speed of the bus; the third interface should be simple, so that the complexity of connecting with the IP core can be reduced. The system-on-chip has a wide range of applications, and different applications have different requirements for the bus. Therefore, the on-chip bus has greater flexibility. First, the data and address widths of most on-chip buses are variable. Second, the interconnection structure of some on-chip buses is variable. For example, the Wishbone bus supports four interconnection modes: point-to-point, data flow, shared bus and crossbar; Third, the arbitration mechanism of some on-chip buses is flexible and variable. For example, the arbitration mechanism of the Wishbone bus can be completely customized by the user. The on-board bus is more rigid and the timing is more demanding. The more common on-chip bus specifications include ARM's AMBA, Silicore's Wishbone, IBM's CoreConnect and Altera's Avalon. The other three types of buses have their own characteristics, and their scope of application is different. The AMBA bus specification has many third-party support due to the widespread use of ARM processors, and has been adopted by more than 90% of ARM's partners, and has become one of the existing interconnection standards widely supported. IBM's CoreConnect is also widely used because of IBM's industry status. Avalon is mainly used in Altera's series FPGAs. The biggest advantage lies in the simplicity of its configuration and can be quickly generated by EDA tools. Although these three kinds of on-chip buses are open standards, they are not free. Wishbone is a truly open and free specification. It was first proposed by Silicore, and is currently maintained by the OpenCores organization. Because of its openness, most of the free IP cores on OpenCores use the Wishbone standard. Wishbone's advantages are not only open, free, and numerous free IP cores, but also simple, flexible, and lightweight. It is especially suitable for interconnecting small IPs within large IPs. In many OpenRISC processor designs, a large number of Wishbone bus specifications are used in the interconnection interface between various modules. Wishbone has been adopted by the OPENCORE alliance and may become an IEEE standard. Therefore, the Wishbone bus is technically simple, flexible, powerful and easy to transplant, and it is all free from an economic point of view, and it is easy to comprehensively promote. We think it is very likely to become the general standard of the SoC on-chip bus in the future, and its prospects are promising. Lattice uses Wishbone bus-based IP core design in MachXO3 and other series of products, including soft cores and some hard cores (Harden I2C, SPI, Timer/Counter). Learning the basic principles of Wishbone is very helpful for us in using and designing IP. As a lightweight on-chip bus, Wishbone is much simpler than AMBA and other buses, and it is very suitable for beginners of on-chip bus to learn. DESCRIPTION
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