Multi-protocol data transmission based on TMS320F206

Digital communication equipment such as all-digital power line carriers usually require multiple channels of voice and data to be transmitted in data channels with limited bandwidth. The data format of such equipment is uncertain, including synchronous data format, asynchronous data format and uncertain non-isochronous Data Format. In addition, the rate of the data interface also changes, and it must be able to adapt to the transmission requirements of different data rates of asynchronous data 300 b / s to 19.2 kb / s and synchronous data 300 b / s to 33.6 kb / s. Indispensable. When the data rate is high, ordinary microprocessors are generally not competent. Due to its special pipeline structure, the DSP chip can better solve problems such as multi-channel multi-protocol high-speed data multiplexing.

1 Design idea

TMS320C2xx is a fixed-point DSP in the TMS320 series of digital signal processors (Digital Signal Process, DSP) produced by TI. The core device of this design is the digital signal processor TMS320F206. He is the only C2xx series with on-chip FLASH DSP chip for memory.

The speed of TMS320F206 can reach 40 MIPS, the fastest execution time of single-cycle instruction can reach 50 ns, and it has abundant on-chip and off-chip resources. Addressable memory space is 224 kB (program space 64 kB, data space 64 kB, I / O space 64 kB, and 32 kB global storage space); on-chip bidirectional access RAM is 544 B, (for 288 B For data, 256 B can be used for program / data); on-chip flash memory is 32 kB; on-chip RAM is 4.5 kB. There are also abundant on-chip peripherals, software programmable timers; software programmable wait state generators for programs, data, and I / O storage spaces; oscillators and phase-locked loops, enabling clock selection: & TImes; 1, & TImes; 2, & TImes; 4 and ÷ 2; synchronous serial port; asynchronous serial port.

Because of its small size, high reliability, and convenient development, CPLD has become the industry's first choice for digital logic circuit design. This design uses Altera's MAX7000 series CPLD chip EPM7128. The number of available gates for EPM7128 is 2 500, the number of macrocells is 128, the number of logic gate array blocks is 8, and the maximum number of user I / Os is 100, which just meets the system's requirements for digital logic circuit design.

MXL1543 is a multi-protocol software programmable data transmission interface chip. It is used in conjunction with MXL1344A multi-protocol software programmable terminal resistance network to enable the data processing unit to quickly and easily meet the user's transmission requirements of different data formats. Flexible selection of V.10, V .11, V.28, V.35 multiple protocols. Therefore, this design selects MXL1543 and MXL1344A to realize multi-protocol interface.

2 hardware implementation

The system consists of the following parts:

(1) The main control part with TMS320F206 as the core.

(2) The logic circuit control part with EPM7128SLC as the core.

(3) Bus drive circuit.

(4) Multi-protocol data interface circuit.

(5) Watchdog circuit.

The following specifically analyzes the function of each part of the circuit.

2.1 Main control circuit with DSP chip as the core

This part of the circuit is composed of TMS320F206, crystal oscillation circuit and JTAG port.

The TMS320F206 port provides 7 simulation pins related to the simulation circuit design, pins 76-82, which are connected to the dual-row 14-pin simulation plug. Through this JTAG port, online simulation debugging can be performed using TI's XDS510 emulator. It must be noted that the simulation plug is a double-row 14-pin, of which the 6th pin should be empty, as a positioning pin. In the figure, EMU0 / 1 is a simulation pin, and a 22 kΩ pull-up resistor is added to ensure the signal rise time, and PD is connected to the power supply. Used for power supply detection, indicating whether the cable is connected and whether the target system is powered on, and the other end is connected to the corresponding end of the DSP. Note that the distance between the simulation head and the TMS320F206 during wiring is not greater than 6 in, otherwise a signal buffer should be added.

It should also be noted that although the TMS320F206 has an on-chip 32 kB FLASH, it cannot be actually used in the debug state. In order to make the simulation system work properly, the RAM for downloading the program must be added to the designed target system. This circuit uses 2 pieces of CYC199 to complete.

Pins 85 to 90 are the pins of the synchronous serial port. In this design, the synchronous serial port is mainly used to process synchronous data. Three types of signals are required for the operation of the synchronous serial port:

The clock signal (CLKX / CLKR) is generated by CPLD and sent; the frame synchronization signal (FSX / FSR) is generated and fed by CPLD; the data signal, the sending pin (DX) is connected to the TTL sending end of the multi-protocol interface chip, receiving The pin (DR) is connected to the TTL receiving end of the multi-protocol interface chip.

The on-chip asynchronous serial port (ASP) can provide convenient serial data communication. There are 4 registers in the chip: asynchronous data sending and receiving register (ADTR), asynchronous serial port control register (ASPCR), I / O status register (IOSR), baud rate division register. There are also two registers inaccessible by programmers: asynchronous serial port transmit shift register (AXSR) and asynchronous serial port receive shift register (ARSR). There are 6 pins TX, RX, IO0, IO1, IO2, IO3. In this design, TX and RX are used to transmit asynchronous data with the host computer, and IO0 ~ IO3 are used as general-purpose I / O ports.

This design uses the general-purpose input pin BIO, general-purpose output pin XF and external interrupt to handle the user's asynchronous data transmission.

The pins D0 ~ D15 and A8 ~ A12 of TMS320F206 are connected to CPLD to realize the expansion of I / O port and other logic functions.

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