USB 3.0: The gospel of high-speed communications within the chip

A major problem with low-power devices such as smart phones and tablets is that the internal communication bus between the chips is small and slow. Most devices are still using older buses such as SDIO (Secure Digital Input Output), GPIO (General Purpose Input Output), HSIC (High-Speed ​​Inter-Chip Connection), and MIPI (Mobile Industrial Processor Interface), but not as commonly used in PCs. PCI Express. Now, the USB-IF organization is preparing to introduce high-speed USB 3.0 into the chip's internal communications. This is the "Super Speed ​​Inter-Chip" (SSIC).

USB-IF is not alone. Instead, it has pulled up the MIPI Alliance and is even ready to directly use the M-PHY physical layer developed by the latter to introduce USB 3.0 into the internal communication of the chip, thus ensuring compatibility and reducing costs. On the other hand, HSIC itself is based on the USB 2.0 standard, so it is reasonable to redevelop the USB 3.0 version.

Unlike PCs, USB 3.0 in portable devices is suitable for very small PCB boards. It is simple to deploy, and it must have lower power consumption and higher energy efficiency. Naturally, it will be very different.

Interestingly, the USB-IF organization is ready to follow the example of the PCI-SIG and divide the number of different channels, such as x1, x2, and x4, to provide different bandwidth configurations. The specific bandwidth is not yet clear, but combined with the theoretical bandwidth of USB 3.0, it is estimated that x1 should be 1.25 Gbps and x4 is 5 Gbps.

The SSIC standard is still in the early stage of preparation, and it is necessary to work out what will be completed next year. Together with the practical process, even if you can see the finished product estimate, it will be 2013.